Along with the advancement of electronic industry, electronic products have been developed with multiple functions and high performances so as to satisfy the requirements of high integration and size miniaturization for semiconductor packages. Further for improving the ability and capacity of a single semiconductor package to achieve size miniaturization, large capacity and high speed for the electronic products, the semiconductor package has been conventionally made as a multi-chip module (MCM), which is capable of effectively reducing the overall size and improving the electrical performance of the package and thus becomes a mainstream package product. The MCM package includes at least two semiconductor chips mounted and vertically stacked on a chip carrier, and is suitably applied to an integrated circuit with high electronic density. Such stacked-chip package structure has been disclosed in U.S. Pat. Nos. 5,545,922, 5,527,740 and 5,366,933.
A conventional method of stacking chips is to package two chips in a back-side to back-side manner, wherein bond pads of the two chips are arranged as a mirroring structure, such that bonding wires connected to the bond pads would not cross and entangle to each other. For example, when two chips having the same functionality are stacked together, one of the chips must be designed with bond pads having a mirroring arrangement relative to bond pads of the other chip. As a result, the fabrication cost of such stacked-chip package structure is relatively higher and increased by fabrication of different specifications for the two chips of the same functionality.
Alternatively, if two chips having the same arrangement of bond pads are stacked together, the bonding wires must be formed in a crossing manner. The crossing wires would be easily subject to short circuit, thus causing a reliability issue. This method is relatively more difficult to implement and leads to difficulty in fabrication.
Accordingly, as shown in FIG. 4, U.S. Pat. No. 6,313,527 has disclosed a semiconductor package to solve the above problems on stacking two chips. In this semiconductor package, a first chip 22 and a second chip 23 are mounted on opposite sides of a lead frame 21 respectively. The lead frame 21 comprises a die pad 21a and a plurality of leads 21b. The first chip 22 is mounted on an upper surface 21a1 of the die pad 21a, and the second chip 23 is attached to a lower surface 21a2 of the die pad 21a. A plurality of bond pads 221, 231 are respectively provided on active surfaces of the first and second chips 22, 23. The bond pads 221 of the first chip 22 are electrically connected to the leads 21b by bonding wires 24. A redistribution layer 25 is formed on the active surface of the second chip 23 and is electrically connected to the leads 21b by bonding wire 24′. Finally, an encapsulant 26 is fabricated to complete the package structure. Since the lead frame 21 is mounted with both the first and second chips 22, 23, the ability and capacity of the package are improved. Moreover, the redistribution layer 25 serves as a wire jumper, such that neither crossing wires nor fabrication of different specifications for chips are required, and the foregoing problems can be solved.
However, the above semiconductor package requires the extra redistribution layer 25. The redistribution layer 25 serving as the wire jumper is a circuit layer with a specific design, which is not commonly available and thus increases the overall design and fabrication costs of the package.
Referring to FIG. 5, another stacked-chip semiconductor package has been disclosed without the use of crossing wires. In this semiconductor package, a first chip 31 and a second chip 32 are mounted on opposite sides of a lead frame 30 respectively. The lead frame 30 comprises a die pad 30a and a plurality of leads 30b. The first chip 31 is attached to a lower surface 30a1 of the die pad 30a. A substrate 33 is mounted on an upper surface 30a2 of the die pad 30a, and the second chip 32 is mounted on the substrate 33. A plurality of bond pads 311, 321 are respectively provided on active surfaces of the first and second chips 31, 32. The bond pads 311 of the first chip 31 are electrically connected to the leads 30b by bonding wires 34. The bond pads 321 of the second chip 32 are firstly electrically connected to bond pads 331 formed on the substrate 33 by bonding wires 35, and then the bond pads 331 of the substrate 33 are electrically connected to the leads 30b by bonding wires 34. Finally, an encapsulant 36 is fabricated to complete the package structure. Similarly, since the lead frame 30 is mounted with both the first and second chips 31, 32, the ability and capacity of the package are improved. Moreover, the bond pads 331 of the substrate 33 serve as a wire jumper, such that the electrical connection of the second chip 32 can be established without using a redistribution method, thereby eliminating the foregoing drawback of the semiconductor package shown in FIG. 4.
However, the above package structure in FIG. 5 requires the extra substrate 33 serving as the wire jumper for the second chip 32, and thus increases the overall fabrication and assembly costs thereof.
Furthermore, in the above package structure, the substrate 33 serving as the wire jumper is firstly attached to the upper surface 30a2 of the die pad 30a of the lead frame 30, and then the second chip 32 is mounted on the substrate 33. The thickness of the substrate 33 is usually larger than that of the chip, which would affect the overall thickness of the package structure. The second chip 32 and the substrate 33 are made of different materials, thereby causing mismatch in coefficient of thermal expansion (CTE) between the second chip 32 and the substrate 33. This results in a significant difference in thermal deformation of expansion and contraction between the second chip 32 and the substrate 33, such that delamination or warpage would easily occur.
Moreover, the lower surface 30a1 of the die pad 30a of the lead frame 30 is mounted with the first chip 31, and the upper surface 30a2 of the die pad 30a is mounted with the substrate 33 and the second chip 32 thereon, such that the upper surface 30a2 of the die pad 30a carriers one more component than the lower surface 30a1 thereof, which forms an unsymmetrical structure. During an encapsulating process, such unsymmetrical structure would cause different upper and lower flow speeds of a resin for making the encapsulant 36 and uneven distribution of the resin. Since the resin is usually a viscous fluid having a low Reynolds number, voids may be generated by incomplete filling of the resin due to the different flow speeds and uneven distribution. And air trapped in the voids may expand and lead to a popcorn effect during a subsequent high-temperature reliability test. This not only damages the package structure but also degrades the yield thereof.
As the first chip 31 and the second chip 32 before being mounted on the die pad 30a of the lead frame 30 have not been tested, and the untested chips 31, 32 are directly subjected to encapsulation, a known good die (KGD) problem may thus be encountered. In other words, even if perfect encapsulation has been performed, the yield of the fabricated packages would still be degraded in the case that the untested first and second chips 31, 32 have defects without the quality thereof being confirmed.
Accordingly, the current various multi-chip packages with the conventional design of the stacked chips would be difficult to eliminate all the above prior-art drawbacks. Therefore, the problem to be solved here is to provide a semiconductor package with stacked chips and a method for fabricating the same so as to reduce a packaging area and improve electrical performance as well as prevent mismatch in CTE and uneven resin flows.